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IDT70P257L

Features: ` True Dual-Ported memory cells which allow simultaneous reads of the same memory location` High-speed access Industrial: 55ns (max.)` Low-power operation IDT70P257/247L Active: 27mW (typ.) Standby: 3.6W (typ.)` Separate upper-byte and lower-byte control for multiplexed bus compatibilit...

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SeekIC No. : 004372071 Detail

IDT70P257L: Features: ` True Dual-Ported memory cells which allow simultaneous reads of the same memory location` High-speed access Industrial: 55ns (max.)` Low-power operation IDT70P257/247L Active: 27mW (typ...

IDT70P257L Data Sheet

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Part Number:
IDT70P257L
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

` True Dual-Ported memory cells which allow simultaneous reads of the same memory location
` High-speed access
  Industrial: 55ns (max.)
` Low-power operation
  IDT70P257/247L
  Active: 27mW (typ.)
  Standby: 3.6W (typ.)
` Separate upper-byte and lower-byte control for multiplexed bus compatibility
` IDT70P257/247 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device
` M/S = VDD for BUSY output flag on Master
  M/S = VSS for BUSY input on Slave
` Input Read Register
` Output Drive Register
` BUSY and Interrupt Flag
` On-chip port arbitration logic
` Full on-chip hardware support of semaphore signaling between ports
` Fully asynchronous operation from either port
` LVTTL-compatible, single 1.8V (±100mV) power supply
` Available in 100 Ball 0.5mm-pitch BGA
` Industrial temperature range (-40°C to +85°C)


Specifications

Symbol Rating

Industrial
Unit
VTERM(2) Terminal Voltage with Respect to GND
-0.5 to VDDMAX +0.3V
V
TBIAS Temperature Under Bias
55 to +125
TSTG Storage Temperature
65 to +150
TJN Junction Temperature
+150
IOUT DC Output Current
50
mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to 20mA for the period over VTERM = VDD + 0.3V.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.


Description

The IDT70P257L is a very low power 8K/4K x 16 Dual-Port Static RAM. The IDT70P257L is designed to be used as a stand-alone 128/64K-bit Dual-Port SRAM or as a combination MASTER/SLAVE Dual- ort SRAM for 32-bit-or-more word systems. Using the IDT MASTER/ SLAVE Dual-Port SRAM approach in 32-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic.

This IDT70P257L provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.

Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 27mW of power.

The IDT70P257L is packaged in a 100 ball 0.5mm- pitch Ball Grid Array. The package is a 1mm thick and designed to fit in wireless handset applications.




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