Features: 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture Four independent 16K x 16 banks 1 Megabit of memory on chip Fast asynchronous address-to-data access time: 15nsUser-controlled input pins included for bank selects Independent port controls with asynchronous address & data busses...
IDT707288S/L: Features: 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture Four independent 16K x 16 banks 1 Megabit of memory on chip Fast asynchronous address-to-data access time: 15nsUser-controlled input ...
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Symbol |
Rating |
Com'l & Ind'l
|
Unit |
Military |
VTERM |
Terminal Voltage with respect to GND |
0.5 to +4.5 |
V |
-0.5 to +7.0 |
TSTG |
Temperature Under Bias |
55 to +125 |
°C |
-65 to +135 |
TSTG |
Storage Temperature |
50 to +50
|
mA |
-65 to +150 |
IOUT |
DC Output Current |
50
|
mA |
50 |
The IDT707288S/L is a high-speed 64K x 16 (1M bit) Bank-Switchable Dual-Ported SRAM organized into four independent 16K x 16 banks. The device has two independent ports with separate control, address, and I/O pins for each port, allowing each port to asynchronously access any 16K x 16 memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via bank select pin inputs under the user's control. Mailboxes are provided to allow interprocessor communication. Interrupts are provided to indicate mailbox writes have occurred.
An automatic power down feature of the IDT707288S/L controlled by the chip enables (CE0 and CE1) permits the on-chip circuitry of each port to enter a very low standby power mode and allows fast depth expansion. The IDT707288S/L offers a maximum address-to-data access time as fast as 15ns, and is packaged in a 100-pin Thin Quad Flatpack (TQFP).