Features: • Ref input is 5V tolerant
• 8 pairs of programmable skew outputs
• Two separate A and B banks for individual control
• Low skew: 185ps same pair, 250ps same bank, 350ps both banks
• Selectable positive or negative edge synchronization on each bank: excellent for DSP applications
• Synchronous output enable on each bank
• Input frequency: 2MHz to 200MHz
• Output frequency: 6MHz to 200MHz
• 3-level inputs for skew and PLL range control
• 3-level inputs for feedback divide selection multiply / divide ratios of (1-6, 8, 10, 12) / (2, 4)
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• Low Jitter: <100ps cycle-to-cycle
• Power-down mode on each bank
• Lock indicator on each bank
• Available in BGA package
Specifications
| Symbol |
Description |
Max |
Unit |
| VDDQ, VDD |
Supply Voltage to Ground |
0.5 to +4.6 |
V |
| VI |
DC Input Voltage |
0.5 to VDD+0.5 |
V |
| |
REF Input Voltage |
0.5 to +5.5 |
V |
| |
Maximum Power
Dissipation |
TA = 85 |
1.1 |
W |
| TA = 55 |
1.9 |
| TSTG |
Storage Temperature Range |
65 to +150 |
|
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
DescriptionThe IDT5V9955 is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5V9955 has sixteen programmable skew outputs in eight banks of 2. The two separate PLLs allow the user to independently control A and B banks. Skew is controlled by 3-level input signals that may be hard-wired to appropriate HIGH-MID-LOW levels.
The feedback input allows divide-by-functionality from 1 to 12 through the use of the xDS[1:0] inputs. This provides the user with frequency multiplication from 1 to 12 without using divided outputs for feedback.When the xsOE pin is held low, all the xbank outputs are synchronously enabled. However, if xsOE is held high, all the xbank outputs xcept x2Q0 and x2Q1 are synchronously disabled. The xLOCK is high when the xbank PLL has achieved phase lock.
Furthermore, when xPE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When xPE is held low, all the xbank outputs are synchronized with the negative edge of REF. The IDT5V9955 has LVTTL outputs with 12mA balanced drive outputs.
IDT5V9955 Data Sheet
