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IDT5V994

Features: • Ref input is 5V tolerant• 4 pairs of programmable skew outputs• Low skew: 200ps same pair, 250ps all outputs• Selectable positive or negative edge synchronization:Excellent for DSP applications• Synchronous output enable• Input frequency: 17.5MHz to ...

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SeekIC No. : 004371903 Detail

IDT5V994: Features: • Ref input is 5V tolerant• 4 pairs of programmable skew outputs• Low skew: 200ps same pair, 250ps all outputs• Selectable positive or negative edge synchronization...

IDT5V994 Data Sheet

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Part Number:
IDT5V994
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Ref input is 5V tolerant
• 4 pairs of programmable skew outputs
• Low skew: 200ps same pair, 250ps all outputs
• Selectable positive or negative edge synchronization:
Excellent for DSP applications
• Synchronous output enable
• Input frequency: 17.5MHz to 133MHz
• Output frequency: 17.5MHz to 133MHz
• 2x, 4x, 1/2, and 1/4 outputs (of VCO frequency)
• 3-level inputs for skew control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• Low Jitter: <200ps cycle-to-cycle
• Available in PLCC and TQFP packages


Pinout

Connection Diagram


Specifications

Symbol
Description
Commercial
& Industrial
Unit
VDDQ, VDD
Supply Voltage to Ground
0.5 to +4.6
V
VI
DC Input Voltage
0.5 to VDD+0.5
V
REF Input Voltage
0.5 to +4.6
V
Maximum Power
Dissipation
 TA = 85°C
0.8
W
 
TSTG
Storage Temperature Range
65 to +150
° C

NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolutemaximum-
rated conditions for extended periods may affect device reliability.


Description

The IDT5V994 is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal.

The IDT5V994 has eight programmable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hardwired to appropriate HIGH-MID-LOW levels. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is held high, all the outputs except 3Q0 and 3Q1 are synchronously disabled. Furthermore, when the PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. The IDT5V994 has LVTTL outputs with 12mA balanced drive outputs.




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