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IDT5V9351

Features: • Fully integrated PLL• Output frequency up to 200MHz• 2.5V and 3.3V Compatible• Compatible with PowerPC™, Intel, and high performance RISC microprocessors• Output frequency configurable• Cycle-to-cycle jitter max. 22ps RMS• Compatible with...

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SeekIC No. : 004371897 Detail

IDT5V9351: Features: • Fully integrated PLL• Output frequency up to 200MHz• 2.5V and 3.3V Compatible• Compatible with PowerPC™, Intel, and high performance RISC microprocessors...

IDT5V9351 Data Sheet

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Part Number:
IDT5V9351
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Fully integrated PLL
• Output frequency up to 200MHz
• 2.5V and 3.3V Compatible
• Compatible with PowerPC™, Intel, and high performance RISC microprocessors
• Output frequency configurable
• Cycle-to-cycle jitter max. 22ps RMS
• Compatible with MPC9351
• Available in TQFP package


Pinout

Connection Diagram


Specifications

Symbol Description
Max
Unit
VCC Supply Voltage Range
0.5 to +4.6
V
VI Input Voltage
0.5 toVCC +3.6
V
VO DC Output Voltage
0.3 to VCC+0.3
V
IIN Input Current
±20
mA
TSTG Storage Temperature
65 to +150
°C
IO DC Output Current
±50
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.




Description

The IDT5V9351 is a high performance, zero delay, low skew, phase-lock loop (PLL) clock driver. It has four banks of configurable outputs. The IDT5V9351 uses a differential PECL reference input and an external feedback input. These features allow the IDT5V9351 to be used as a zero delay, low skew fan-out buffer. REF_SEL allows selection between PECL input or TCLK, a CMOS clock driver input.

If PLL_EN is set to low and REF_SEL to high, it will bypass the PLL. By doing so, the IDT5V9351 will be in clock buffer mode. Any clock applied to TCLK will be divided down to four output banks. When PLL_EN is set high, PLL is enabled. Any clock applied to TCLK will be clocked in both phase and frequency to FBIN. PECL clock is activated by setting REF_SEL to low.




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