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IDT5T9050

Features: • Optimized for 2.5V LVTTL• Guaranteed Low Skew < 25ps (max)• Very low duty cycle distortion < 300 (max)• High speed propagation delay < 1.8ns. (max)• Up to 200MHz operation• Very low CMOS power levels• Hot insertable and over-voltage to...

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SeekIC No. : 004371875 Detail

IDT5T9050: Features: • Optimized for 2.5V LVTTL• Guaranteed Low Skew < 25ps (max)• Very low duty cycle distortion < 300 (max)• High speed propagation delay < 1.8ns. (max)•...

IDT5T9050 Data Sheet

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Part Number:
IDT5T9050
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

• Optimized for 2.5V LVTTL
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion < 300 (max)
• High speed propagation delay < 1.8ns. (max)
• Up to 200MHz operation
• Very low CMOS power levels
• Hot insertable and over-voltage tolerant inputs
• 1:5 fanout buffer
• 2.5V VDD
• Available in TSSOP package


Application

• Clock and signal distribution


Pinout

Connection Diagram


Specifications

Symbol Description
Max
Unit
VDD Power Supply Voltage(2)
0.5 to +3.6
V
VI Input Voltage
0.5 to +3.6
V
VO Output Voltage(3)
0.5 to VDD +0.5
V
TSTG Storage Temperature
65 to +165
°C
TJ Junction Temperature
150
°C

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.




Description

The IDT5T9050 2.5V single data rate (SDR) clock buffer is a single-ended input to five single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. Multiple power and grounds reduce noise.




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