Features: • Common features: Low input and output leakage 1A (max.) CMOS power levels True TTL input and output compatibility VOH = 3.3V (typ.) VOL = 0.3V (typ.) Meets or exceeds JEDEC standard 18 specifications Product available in Radiation Tolerant and Radiation Enhanced versions Mi...
IDT54FCT823AT: Features: • Common features: Low input and output leakage 1A (max.) CMOS power levels True TTL input and output compatibility VOH = 3.3V (typ.) VOL = 0.3V (typ.) Meets or exceeds JEDEC sta...
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Features: • IDT54/74FCT646 equivalent to FAST™speed;• IDT54/74FCT646A 30% faster...
Features: • IDT54/74FCT646 equivalent to FAST™speed;• IDT54/74FCT646A 30% faster...
Symbol | Rating | Commercial | Military | Unit |
VTERM | Terminal Voltage with Respect to GND |
0.5 to +7.0 | 0.5 to +7.0 | V |
VTERM | Terminal Voltage with Respect to GND |
-0.5 to VCC +0.5 | 0.5 to VCC +0.5 | V |
TA | Operating Temperature |
0 to +70 | 55 to +125 | °C |
TBIAS | Temperature Under Bias |
55 to +125 | 65 to +135 | °C |
TSTG |
Storage Temperature |
55 to +125 | 65 to +150 | °C |
PT | Power Dissipation | 0.5 | 0.5 | W |
IOUT |
DC Output Current |
60 to +120 | 60 to +120 | mA |
The IDT54FCT823AT series is built using an advanced dual metal CMOS technology. The FCT82xT series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The FCT821T are buffered, 10-bit wide versions of the popular FCT374T function. The FCT823T are 9-bit wide buffered registers with Clock Enable ( EN) and Clear ( CLR) ideal for parity bus interfacing in high-performance microprogrammed systems.
The IDT54FCT823AT are 8-bit buffered registers with all the FCT823T controls plus multiple enables ( OE1, OE2, OE3) to allow multiuser control of the interface, e.g., CS, DMA and RD/ WR. They are ideal for use as an output port requiring high IOL/IOH.The IDT54FCT823AT high-performance interface family can drive large capacitive loads, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in high-impedance state.