IDT54FCT388915T100PYB

NOTES:                                                                                                              3052 tbl 02
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device.  This is a stress ratin only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  Exposure to absolute maximum rating conditions for ex- tended periods may affect reliability.
2.Vcc  terminals.
3.Input terminals.
4.Output and I/O terminals.

The IDT54FCT388915T100PYB uses phase-lock loop technol- ogy to lock the frequency and phase of outputs to the input reference clock.  It provides low skew clock distribution for high performance PCs and workstations.  One of the outputsis fed back to the PLL at the FEEDBACK input resulting in essentially zero delay across the device.  The PLL consists of the phase/frequency detector, charge pump, loop filter and VCO.  The VCO is designed for a 2Q operating frequency range of 40MHz to f2Q Max.

The IDT54FCT388915T100PYB provides 8 outputs with 350psskew.  The  Q5 output is inverted from the Q outputs.  The 2Q
runs at twice the Q frequency and Q/2 runs at half the Q frequency.

The FREQ_SEL control provides an additional + 2 option in the output path. PLL _EN allows bypassing of the PLL, which s useful in static test modes.  When PLL_EN is low, SYNC nput may be used as a test clock.  In this test mode, the input frequency is not limited to the specified range and the polarity of outputs is complementary to that in normal operation (PLL_EN = 1).  The LOCK output attains logic HIGH when the PLL is in steady-state phase and frequency lock.  When OE/ RST is low, all the outputs are put in high impedance state and
registers at Q, Q and Q/2 outputs are reset.

The IDT54FCT388915T100PYB requires one external loop filter component as recommended in Figure 3.