IDT54FCT162H501CT

The IDT54FCT162H501CT 18-bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power 18-bit registered bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by outputenable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow,the device operates in transparent mode when LEAB is HIGH.When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level.

If LEAB of the IDT54FCT162H501CT is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. OEAB is the output enable for the B port. Data flow from the B port to the A port is similar but requires using OEBA,LEBA and CLKBA. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin.The FCT16501AT/CT/ET are ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers.

The IDT54FCT162H501CT have balanced output drive with current limiting resistors. This offers low ground bounce,minimal undershoot, and controlled output fall timesreducing the need for external series terminating resistors. The FCT162501AT/CT/ET are plug-in replacements for the IDT54FCT162H501CT for on-board bus interface applications.The IDT54FCT162H501CT have "Bus Hold" which retains the input's last state whenever the input goes to high impedance. This prevents "floating" inputs and eliminates the need for pull-up/down resistors.