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IDT49FCT805BTDPY

Features: •0.5 MICRON CMOS Technology• Guaranteed low skew < 500ps (max.)• Very low duty cycle distortion < 600ps (max.)• Low CMOS power levels• TTL compatible inputs and outputs• TTL level output voltage swings• High drive: -32mA IOH, +48mA IOL̶...

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SeekIC No. : 004371695 Detail

IDT49FCT805BTDPY: Features: •0.5 MICRON CMOS Technology• Guaranteed low skew < 500ps (max.)• Very low duty cycle distortion < 600ps (max.)• Low CMOS power levels• TTL compatible in...

IDT49FCT805BTDPY Data Sheet

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Part Number:
IDT49FCT805BTDPY
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

•0.5 MICRON CMOS Technology
• Guaranteed low skew < 500ps (max.)
• Very low duty cycle distortion < 600ps (max.)
• Low CMOS power levels
• TTL compatible inputs and outputs
• TTL level output voltage swings
• High drive: -32mA IOH, +48mA IOL
• Two independent output banks with 3-state control
• 1:5 fanout per bank
• "Heartbeat" monitor output
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• Available in the following packages:
Commercial: QSOP, SOIC, SSOP
Military: CERDIP, LCC


Pinout

Connection Diagram


Specifications

Symbol Description Max Unit
VTERM Terminal Voltage with Respect to GND 0.5 to +7 V
TSTG Storage Temperature 65 to +150
IOUT DC Output Current 60 to +120 mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.


Description

This buffer/clock driver of the IDT49FCT805BTDPY is built using advanced dual metal CMOS technology. The FCT805T is a non-inverting clock driver consisting of two banks of drivers. Each bank drives five output buffers from a standard TTL compatible input. This part has extremely low output skew, pulse skew, and package skew. The device has a "heart-beat" monitor for diagnostics and PLL driving. The monitor output is identical to all other outputs and complies with the output specifications in this document.

The IDT49FCT805BTDPY is designed for fast, clean edge rates to provide accurate clock distribution in high speed systems.




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