Features: 64-bit wide Flow-thruEDC(TM) Separate System and Memory Data Input/Output Buses - Error Detect Time: 10ns - Error Correct Time: 15ns Corrects all single bit errors; Detects all double bit errors and some multiple bit errors Configurable 16-deep bus read/write FIFOs with flags Simultaneou...
IDT49C466A: Features: 64-bit wide Flow-thruEDC(TM) Separate System and Memory Data Input/Output Buses - Error Detect Time: 10ns - Error Correct Time: 15ns Corrects all single bit errors; Detects all double bit ...
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Features: • FastDetect Correct - IDT49C460E 10ns (max.) 14ns (max.) - IDT49C460D 12ns (max.)...
Features: • FastDetect Correct - IDT49C460E 10ns (max.) 14ns (max.) - IDT49C460D 12ns (max.)...
Symbol | Rating | Com'l. | Unit |
VCC | Power Supply Voltage | 0.5 to +7.0 | V |
VTERM | Terminal Voltage with Respect to Ground | 0.5 to VCC + 0.5 |
V |
TBIAS | Temperature Under Bias | 55 to +125 | |
TSTG |
Storage Temperature | 55 to +125 | |
IOUT | DC Output Current | 30 | mA |
The IDT49C466A 64-bit Flow-thruEDC is a high-speed error detection and correction unit that ensures data integrity in memoy stems. The flow-thru architecture, with separate
system and memory data buses, is ideally suited for pipelined memory systems.
Implementing a modified Hamming code, the IDT49C466A corrects all single bit hard and soft errors, and detects all double bit errors. The read/write FIFOs can store up to sixteen words. FIFO full and empty flags indicate whether additional data can be written to or read from the EDC.
Check bit generation for partial word writes on byte bound-aries is supported on the IDT49C466A.
Diagnostic features include a check bit register, syndrome registers, a four bit error counter which logs up to 15 errors,and an error data register which stores the complete error data
word. Parity can be generated and checked on the system bus by the IDT49C466A.