IDT23S08E

Features: • Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 200MHz operating frequency• Distributes one clock input to two banks of four outputs• Separate output enable for each output bank• External feedback (FBK) pin is used to synchronize the ou...

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IDT23S08E Picture
SeekIC No. : 004371647 Detail

IDT23S08E: Features: • Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 200MHz operating frequency• Distributes one clock input to two banks of four outputs• Separate...

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Part Number:
IDT23S08E
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/7/15

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Product Details

Description



Features:

• Phase-Lock Loop Clock Distribution for Applications ranging
   from 10MHz to 200MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback (FBK) pin is used to synchronize the outputs
   to the clock input
• Output Skew <200 ps
• Low jitter <200 ps cycle-to-cycle
• 1x, 2x, 4x output options (see table):
IDT23S08E-1 1x
IDT23S08E-2 1x, 2x
IDT23S08E-3 2x, 4x
IDT23S08E-4 2x
IDT23S08E-1H, -2H, and -5H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Spread spectrum compatible
• Available in SOIC and TSSOP packages



Pinout

  Connection Diagram


Specifications

 
Symbol Rating Max. Unit
VDD Supply Voltage Range 0.5 to +4.6 V
VI (2) Input Voltage Range (REF) 0.5 to +5.5 V
VI Input Voltage Range (except REF) 0.5 toVDD+0.5 V
IIK (VI < 0) Input Clamp Current 50 mA
IO (VO = 0 to VDD) Continuous Output Current ±50 mA
VDD or GND Continuous Current ±100 mA
TA = 55°C (in still air)(3) Maximum Power Dissipation 0.7 W
TSTG Storage Temperature Range 65 to +150 °C
Operating Temperature Commercial Temperature Range 0 to +70 °C
Operating Temperature Industrial Temperature Range -40 to +85 °C

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
  cause permanent damage to the device. This is a stress rating only and functional
  operation of the device at these or any other conditions above those indicated in the
  operational sections of this specification is not implied. Exposure to absolute maximum
  rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
  clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
  of 150°C and a board trace length of 750 mils.




Description

The IDT23S08E is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 200MHz.

The IDT23S08E has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing purposes. In the absence of an input clock, the IDT23S08E enters power down. In this mode, the device will draw less than 12A for Commercial Temperature range and less than 25A for Industrial temperature range, and the outputs are tri-stated.

The IDT23S08E is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. (See available options table.)

The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs.

The IDT23S08E is characterized for both Industrial and Commercial operation.




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