Features: • Phase-Lock Loop Clock Distribution• 10MHz to 133MHz operating frequency• Distributes one clock input to one bank of five and one bank of four outputs• Separate output enable for each output bank• Output Skew < 250ps• Low jitter <200 ps cycle-to...
IDT2309A: Features: • Phase-Lock Loop Clock Distribution• 10MHz to 133MHz operating frequency• Distributes one clock input to one bank of five and one bank of four outputs• Separate ou...
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Symbol | Rating | Max. | Unit |
VDD | Supply Voltage Range | 0.5 to +4.6 | V |
VI(2) | Input Voltage Range (REF) | 0.5 to +5.5 | V |
VI | Input Voltage Range (except REF) |
0.5 to VDD+0.5 | V |
IIK (VI < 0) | Input Clamp Current | 50 | mA |
IO (VO = 0 to VDD) | Continuous Output Current | ±50 | mA |
VDD or GND | Continuous Current | ±100 | mA |
TA = 55 (in still air)(3) |
Maximum Power Dissipation | 0.7 | W |
TSTG | Storage Temperature Range | 65 to +150 | |
Operating Temperature |
Commercial Temperature Range |
0 to +70 | |
Operating Temperature |
Industrial Temperature Range |
-40 to +85 |
The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer,designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.
The IDT2309A is a 16-pin version of the IDT2305A. The IDT2309A accepts one reference input, and drives two banks of four low skew clocks.The -1H version of this device operates up to 133MHz frequency and has higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT2309A enters power down. In this mode, the device will draw less than 12µA for Commercial Temperature range and less than 25µA for Industrial temperature range, and the outputs are tri-stated.