ICS9DB306

Supply Voltage, V_CC.................................. 4.6V
Inputs, VI -0.5V to V_CC ............................... + 0.5V
Outputs, I_O
Continuous Current   .................................50mA
Surge Current.................................... 100mA
Package Thermal Impedance, _JA   ...................49.8°C/W (0 lfpm)
Storage Temperature, T_STG   .......................-65°C to 150°C

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

The ICS9DB306 is a high performance 1-to-6 Differential-to LVPECL Jitter Attenuator designed for use in PCI Express™ systems. In some PCI Express™ systems, such as those found in desktop PCs, the PCI Express™ clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a zero delay buffer may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS9DB306 has 2 PLL bandwidth modes. In low bandwidth mode, the PLL loop BW is about 500kHz and this setting will attenuate much of the jitter from the reference clock input while being high enough to pass a triangular input spread spectrum profile. There is also a high bandwidth mode of the ICS9DB306 which sets the PLL bandwidth at 1MHz which will pass more spread spectrum modulation.

For serdes which have x30 reference multipliers instead of x25 multipliers, 5 of the 6 PCI Express™ outputs (PCIEX1:5) can be set for 125MHz instead of 100MHz by configuring the appropriate frequency select pins (FS0:1). Output PCIEX0 will always run at the reference clock frequency (usually 100MHz) in desktop PC PCI Express™ Applications.