Features: • CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications• PLL or bypass mode/PLL can dejitter incoming clock• Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's• Spread Spectrum Compatible/tracks spreading input clock for lo...
ICS9DB102: Features: • CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications• PLL or bypass mode/PLL can dejitter incoming clock• Selectable PLL bandwidth/minimizes jitt...
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Symbol |
Parameter |
Min |
Max |
Units |
VDDA |
3.3V Core Supply Voltage |
VDD + 0.5V |
V | |
VDD |
3.3V Output Supply Voltage |
GND - 0.5 |
VDD + 0.5V |
V |
Ts |
Storage Temperature |
-65 |
150 |
°C |
Tambient |
Ambient Operating Temp |
0 |
70 |
°C |
Tcase |
Case Temperature |
115 |
°C | |
ESD prot |
Input ESD protection human body model |
2000 |
V |
The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS K409/CK410-compliant main clock generator such as the ICS952601 or ICS954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the ICS9DB102 suitable for Express Card applications.