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ICS93V855

Features: • Low skew, low jitter PLL clock driver• External feedback pins for input to output synchronization• Spread Spectrum tolerant inputs• With bypass mode mux• Operating frequency 60 to 170 MHzPinoutSpecificationsSupply Voltage: (VDD & AVDD) . . . . . . . . ...

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ICS93V855: Features: • Low skew, low jitter PLL clock driver• External feedback pins for input to output synchronization• Spread Spectrum tolerant inputs• With bypass mode mux• Op...

ICS93V855 Data Sheet

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Part Number:
ICS93V855
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Low skew, low jitter PLL clock driver
• External feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• With bypass mode mux
• Operating frequency 60 to 170 MHz


Pinout

Connection Diagram


Specifications

Supply Voltage: (VDD & AVDD) . . . . . . . . . . . . . . . . . . . .-0.5V to 3.6V
                              (VDDI) . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.6V
Logic Inputs: VI . . . . . . . . . . . . . . . . . . . . .VSS 0.5 V to VDD +0.5 V
Logic Outputs: VO. . . . . . . . . . . . . . . . . . . .VSS 0.5 V to VDD +0.5 V
Input clamp current: IIK (VI < 0 or VI > VDD) . . . . . . . . . . . .+/- 50mA
Output clamp current: IOK (VO < 0 or VO > VDD)  . . . . . . . .  +/- 50mA
Continuous output current: IO (VO = 0 to VDD)  . . . . . . . . . .+/- 50mA
Storage Temperature . . . . . . . . . . . . . . . . . . .  . .65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.




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