ICS9179-06

Features:

·Zero delay buffer, 16 outputs
·Supports up to four SDRAM DIMMS
· Wide PLL loop bandwidth makes this part ideal in Spread Spectrum applications.
· Skew Input to FB_IN ±250ps default, with selectable skew -2.7, +2.0, -0.7ns nominal.
· Synchronous clocks skew matched to 250 ps window on output.
· 33 to 133MHz input or output frequency.
· I²C Serial Configuration interface to allow individual clocks to be stopped, or selectable delays.
· Multiple VDD, VSS pins for noise reduction
· Slew rate 1.5V/ns into 30pF.
· VDD = 3.3 ±5%, 0 to 70°C
· All outputs (0:15) tristate with OE low (FB_OUT stays running).
·48-Pin SSOP package

Pinout




Specifications

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .  . . .  . . .  . . .  . .7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . .. G_ND -0.5 V to V_DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . .  .  . .  . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C


Description

The ICS9179-06 generates low skew clock buffers required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. An output enable is provided for testability.

The ICS9179-06 is a buffer with low output to output skew. This is a zero delay buffer device, using an internal PLL. This buffer can be used for phase synchronization to a master clock. With the wide PLL loop BW, this buffer is compatible to Spread Spectrum input clocks from clock generator products such as the ICS9148-27.

The individual clock outputs of the ICS9179-06 are addressable through I²C to be enabled, or stopped in a low state for reduced EMI when the lines are not needed. The device defaults to zero-delay mode, but can be programmed with I2C for selectable delays -2.7, +2.0, -0.7 ns (nominal target values).