ICS557-01

Features: • Supports PCI-ExpressTM HCSL Outputs 0.7 V current mode differential pair• Supports LVDS Output Levels• Packaged in 8-pin SOIC• Available in Pb (lead) free package• Operating voltage of 3.3 V• Low power consumption• Input frequency of 25 MHzR...

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ICS557-01 Picture
SeekIC No. : 004370822 Detail

ICS557-01: Features: • Supports PCI-ExpressTM HCSL Outputs 0.7 V current mode differential pair• Supports LVDS Output Levels• Packaged in 8-pin SOIC• Available in Pb (lead) free package...

floor Price/Ceiling Price

Part Number:
ICS557-01
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/25

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Product Details

Description



Features:

• Supports PCI-ExpressTM HCSL Outputs 0.7 V current mode differential pair
• Supports LVDS Output Levels
• Packaged in 8-pin SOIC
• Available in Pb (lead) free package
• Operating voltage of 3.3 V
• Low power consumption
• Input frequency of 25 MHz
• Short term jitter 100 ps (peak-to-peak)
• Output Enable via pin selection
• Industrial temperature range available



Pinout

  Connection Diagram


Specifications

Supply Voltage, VDD, VDDA                                               5.5 V
All Inputs and Outputs                              -0.5 V to VDD+0.5 V
Ambient Operating Temperature (commercial)      0 to +70°C
Ambient Operating Temperature (industrial)      -40 to +85°C
Storage Temperature                                       -65 to +150°C
Junction Temperature                                                   125°C
Soldering Temperature                                                 260°C
ESD Protection (Input)                                2000 V min. (HBM)



Description

The ICS557-01 is a clock chip designed for use in PCI-Express Cards as a clock source. It provides a pair of differential outputs at 100 MHz in a small 8-pin SOIC package.

Using ICS' patented Phase-Locked Loop (PLL) techniques, the device takes a 25 MHz crystal input and produces HCSL (Host Clock Signal Level) differential outputs at 100 MHz clock frequency. LVDS signal levels of the ICS557-01 can also be supported via an alternative termination scheme.




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