ICS552-01 (B mode)

Features:

• Up to 200 MHz clock input/output at 3.3 V
• Low skew of 250 ps maximum for any bank of four
• Inputs can be connected together for a 1 to 8 buffer
   with 250 ps skew between any outputs
• Non-inverting buffer mode
• Ideal for clock networks
• Output Enable mode tri-states outputs
• Full CMOS output swing with 25 mA output drive
   capability at TTL levels
• Advanced, low power, sub-micron CMOSprocess


Pinout




Specifications

Parameter	Condition	Min.	Typ.	Max.	Units
Supply Voltage, VDD	Referenced to GND			7	V
Inputs	Referenced to GND	-0.5		VDD+0.5	V
Clock Outputs	Referenced to GND	-0.5		VDD+0.5	V
Storage Temperature		-65		150	°C
Soldering Temperature	Max 10 seconds			260	°C
Junction Temperature				125	°C

Description

The ICS552-01 (B mode)  produces 8 low-skew copies of the multiple input clock or fundamental, parallel-modecrystal. Unlike other clock drivers, these parts do not require a separate oscillator for the input. Using ICS' patented Phase-Locked Loop (PLL) to multiply the input frequency, it is ideal for generating and distributing multiple high-frequency clocks. This is a single chip used for 3 different applications:
1) ICS552-01 (A mode) - an Oscillator mutilpier
2) ICS552-01 (B mode) - a Dual 1:4 buffer
3) ICS552-01 (C mode) - a 1:8 Oscillator buffer