ICS548-03

The ICS548-03 is a low cost, low skew, high performance general-purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-2. Using our patented analog Phase-Locked Loop (PLL) techniques, the device operates from a frequency range from 10 MHz to 120 MHz in the PLL mode, and up to 160 MHz in the non-PLL mode.

In applications that to need maintain low phase noise in the clock tree, the non-PLL (when S3=S2=1) mode should be used.

This chip of the ICS548-03 is not a zero delay buffer. Many applications may be able to use the ICS527 for zero delay dividers.