ICS527-04

Features: • Packaged as 28-pin SSOP (150 mil body)• Synchronizes fractional clocks rising edges• CMOS in to PECL out• PECL in to PECL out• Pin selectable dividers• Zero input to output skew• User determines the output frequency - no software needed• ...

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ICS527-04 Picture
SeekIC No. : 004370799 Detail

ICS527-04: Features: • Packaged as 28-pin SSOP (150 mil body)• Synchronizes fractional clocks rising edges• CMOS in to PECL out• PECL in to PECL out• Pin selectable dividers•...

floor Price/Ceiling Price

Part Number:
ICS527-04
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

• Packaged as 28-pin SSOP (150 mil body)
• Synchronizes fractional clocks rising edges
• CMOS in to PECL out
• PECL in to PECL out
• Pin selectable dividers
• Zero input to output skew
• User determines the output frequency - no software needed
• Slices frequency or period
• Input clock frequency of 1.5 MHz - 200 MHz
• Output clock frequencies up to 160 MHz
• Very low jitter
• Duty cycle of 45/55
• Operating voltage of 3.3 V
• Advanced, low power CMOS process



Pinout

  Connection Diagram


Specifications

Supply Voltage, VDD                                    7 V
All Inputs and Outputs        -0.5 V to VDD+0.5 V
Ambient Operating Temperature    0 to +70°C
Storage Temperature              -65 to +150°C
Junction Temperature                          125°C
Soldering Temperature                         260°C



Description

The ICS527-04 Clock Slicer is the most flexible way to generate an output clock from an input clock with zero  skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz.

The ICS527-04 aligns rising edges on PECLIN with FBPECL at a ratio determined by the reference and feedback dividers.

For other PECL output clocks, see the ICS507-01, ICS525-03, or the MK3707. For PECL in and CMOS out, see the ICS527-02. For CMOS in and PECL out with zero delay, use the ICS527-03.




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