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ICS527-02

Features: • Packaged as 28-pin SSOP (150 mil body)• Synchronizes fractional clocks rising edges• PECL IN to CMOS OUT• Pin selectable dividers• Zero input to output skew• User determines the output frequency-no softwareneeded• Slices frequency or periodR...

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SeekIC No. : 004370797 Detail

ICS527-02: Features: • Packaged as 28-pin SSOP (150 mil body)• Synchronizes fractional clocks rising edges• PECL IN to CMOS OUT• Pin selectable dividers• Zero input to output skew...

ICS527-02 Data Sheet

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Part Number:
ICS527-02
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

• Packaged as 28-pin SSOP (150 mil body)
• Synchronizes fractional clocks rising edges
• PECL IN to CMOS OUT
• Pin selectable dividers
• Zero input to output skew
• User determines the output frequency-no software
needed
• Slices frequency or period
• Input clock frequency of 1.5 MHz to 200 MHz
• Output clock frequencies from 2.5 MHz to 160 MHz
• Very low jitter
• Duty cycle of 45/55
• Operating voltage of 3.3 V
• Advanced, low-power CMOS process
• Industrial temperature version available


Pinout

Connection Diagram




Specifications

Supply Voltage, VDD                                            7 V
All Inputs and Outputs                -0.5 V to VDD+0.5 V
Ambient Operating Temperature         -40 to +85°C
Storage Temperature                       -65 to +150°C
Junction Temperature                                    125°C
Soldering Temperature                                  260°C


Description

The ICS527-02 Clock Slicer is the most flexible way to generate a CMOS output clock from a PECL input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. A SYNC pulse indicates when the rising clock edges are aligned with zero skew. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz.

The ICS527-02 aligns rising edges on PECLIN with FBIN at a ratio determined by the reference and feedback dividers.

For a PECL input and output clock with zero delay, use the ICS527-04.

For a CMOS input and PECL output with zero delay, use the ICS527-03.




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