Features: • 3-channel 8-bit analog-to-digital conversion up to 165 MHz• Direct connection to analog input data (no external pre-amplifier circuit needed)• Video amplifier: 500-MHz analog bandwidth, software-adjustable gain• Dynamic Phase Adjust (DPA) for software-adjustable...
ICS1531: Features: • 3-channel 8-bit analog-to-digital conversion up to 165 MHz• Direct connection to analog input data (no external pre-amplifier circuit needed)• Video amplifier: 500-MHz ...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Item |
Rating |
VDD, VDDQ (measured with respect to VSS) | 4.3 V |
Digital Inputs | VSS -0.3 V to +5.5 V |
Digital Outputs | VSSQ -0.3 V to VDDQ +0.3 V |
Analog Inputs | VSS -0.3 V to +5.5 V |
Analog Outputs | VSSA -0.3 V to VDDA +0.3 V |
Storage Temperature | -65 to +150 |
Junction Temperature | 175 |
Soldering Temperature | 260 |
Power Dissipation | See Section 9.3, "Power Values" |
The ICS1531 is a high-performance, cost-effective,3-channel, 8-bit analog-to-digital converter with an integrated line-locked clock generator. It is part of a family of chips intended for high-resolution video applications that use analog inputs, such as LCD monitors, LCD projectors,plasma displays, and projection TVs. Using ICS's low-voltage CMOS mixed-signal technology, the ICS1531 is an effective data-capture solution for resolutions from VGA to UXGA.
The ICS1531 offers analog-to-digital data conversion and synchronized pixel clock generation at speeds of 100, 140, or 165 MHz (or mega samples per second, MSPS). The Dynamic Phase Adjust (DPA) circuitry allows end-user control over the pixel clock phase, relative to the recovered sync signal and analog pixel data. Either the internal pixel clock can be used as a capture clock input to the analog-to-digital converters or an external clock input can be used. The ICS1531 provides either one or two 24-bit pixels per clock. An ADCSYNC output pin provides recovered HSYNC from the pixel clock phase-locked-loop (PLL) divider chain output, which can be used to synchronize display enable output.
A clamp signal of the ICS1531 can be generated internally or provided through the CLAMP pin. A high-bandwidth video amplifier with adjustable gain allows fine tuning of the analog signal.The advanced PLL uses an internal programmable feedback divider. Two additional, independent programmable PLLs,each with spread-spectrum functionality, support memory and panel clock requirements.