Features: • 8-Bit, mP Bus Compatible - Multiplexed or Direct Addressing• Regulated Oscillator Supply Ensures Frequency Stability and Low Power• Time From 1/100 Seconds to 99 Years• Software Selectable 12/24 Hour Format• Latched Time Data Ensures No Roll Over During Re...
ICM7170: Features: • 8-Bit, mP Bus Compatible - Multiplexed or Direct Addressing• Regulated Oscillator Supply Ensures Frequency Stability and Low Power• Time From 1/100 Seconds to 99 Years&...
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The ICM7170 real time clock is a microprocessor bus compatible peripheral, fabricated using Intersil's silicon gate CMOS LSl process. An 8-bit bidirectional bus is used for the data I/O circuitry. The clock is set or read by accessing the 8 internal separately addressable and programmable counters from 1/100 seconds to years. The counters are controlled by a pulse train divided down from a crystal oscillator circuit,and the frequency of the crystal is selectable with the onchip command register. An extremely stable oscillator frequency is achieved through the use of an on-chip
regulated power supply. The ICM7170 access time (tACC) of 300ns eliminates the need for wait states or software overhead with most microprocessors. Furthermore, an ALE (Address Latch Enable) input is provided for interfacing to microprocessors with a multiplexed address/data bus. With these two special features, the ICM7170 can be easily interfaced to any available microprocessor.
The ICM7170 generates two types of interrupts, periodic and alarm. The periodic interrupt (100Hz, 10Hz, etc.) can be
programmed by the internal interrupt control register to provide 6 different output signals. The alarm interrupt is set by loading an on-chip 51-bit RAM that activates an interrupt output through a comparator. The alarm interrupt occurs when the real time counter and alarm RAM time are equal. A status register is available to indicate the interrupt source.
An on-chip Power Down Detector eliminates the need for external components to support the battery back-up function. When a power down or power failure occurs,internal logic switches the on-chip counters to battery backup operation. Read/write functions of the ICM7170 become disabled and operation is limited to time-keeping and interrupt generation, resulting in low power consumption.
Internal latches prevent clock roll-over during a read cycle.Counter data is latched on the chip by reading the 100th-seconds counter and is held indefinitely until the counter is read again, assuring a stable and reliable time value.