Features: • 184-pin Registered 8-Byte Dual-In-Line DDR-I SDRAM Module for PC and Server main memory applications• One bank 32M × 72, 64M x 72, and two bank 64M x 72, 128M × 72 organization• JEDEC standard Double Data Rate Synchronous DRAMs (DDR-I SDRAM) with a single + 2.5 V (± 0...
HYS 72Dxx0xxGR-8-A: Features: • 184-pin Registered 8-Byte Dual-In-Line DDR-I SDRAM Module for PC and Server main memory applications• One bank 32M × 72, 64M x 72, and two bank 64M x 72, 128M × 72 organizati...
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Features: • 184-pin Registered 8-Byte Dual-In-Line DDR-I SDRAM Module for PC and Server main...
Parameter |
Symbol |
Limit Values |
Unit | |
min. |
max. | |||
Input / Output voltage relative to VSS |
VIN, VOUT |
0.5 |
3.6 |
V |
Power supply voltage on VDD/VDDQ to VSS |
VDD, VDDQ |
0.5 |
3.6 |
V |
Storage temperature range |
TSTG |
-55 |
+150 |
|
Power dissipation (per SDRAM component) |
PD |
- |
1 |
W |
Data out current (short circuit) |
IOS |
- |
150 |
mA |
The HYS 72Dxx0xxGR-8-A are industry standard 184-pin 8-byte Dual in-lineMemory Modules (DIMMs) organized as 32M × 72 (256MB), 64M × 72 (512MB) and 128M × 72 (1GB). The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes of the HYS 72Dxx0xxGR-8-A are available to the customer.