HYB39S512160AT(L)

Features:

• Fully Synchronous to Positive Clock Edge
• 0 to 70°C operating temperature
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2 & 3
• Programmable Wrap Sequence: Sequential or Interleave
• Programmable Burst Length: 1, 2, 4, 8 and full page
• Multiple Burst Read with Single Write Operation
• Automatic and Controlled Precharge Command
• Data Mask for Read / Write control (*4, *8)
• Data Mask for byte control (*16)
• Auto Refresh (CBR) and Self Refresh
• Power Down and Clock Suspend Mode
• 8192 refresh cycles / 64 ms (7,8 s)
• Random Column Address every CLK ( 1-N Rule)
• Single 3.3 V ± 0.3 V Power Supply
• LVTTL Interface versions
• Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)


Pinout




Description

The HYB39S512160AT(L) are four bank Synchronous DRAM's organized as 4 banks * 32MBit *4, 4 banks * 16MBit *8 and 4 banks * 8Mbit *16 respectively. These synchronous devices achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with INFINEON's advanced 0.14 m
512MBit DRAM process technology.

The device HYB39S512160AT(L) is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device HYB39S512160AT(L).

Auto Refresh (CBR) and Self Refresh operation are supported. These devices HYB39S512160AT(L) operates with a single 3.3 V ± 0.3 V power supply. All 512Mbit components are housed in P-TSOPII-54 packages.