HYB39S16800BT

The HYB39S16800BTare dual bank Synchronous DRAM' s based on the die revisions "D", & "E" and organized as 2 banks x 2MBit x4, 2 banks x 1MBit x8 and 2 banks x 512kbit x16 respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz byemploying a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS' advanced 16MBit DRAM process technology.

The device HYB39S16800BT is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.

Operating the two memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 125 MHz is possible depending on burst length, CAS latency and speed grade of the device HYB39S16800BT.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices HYB39S16800BT operate with a single 3.3V +/- 0.3V power supply and are available in TSOPII packages.

These Synchronous DRAM devices HYB39S16800BT are available with LV-TTL interfaces.