HYB39S13620TQ-7

The HYB39S13620TQ-7 are dual bank Synchronous Graphics DRAM's (SGRAM) organized as 2 banks x 256 Kbit x  32 with built-in graphics features. These synchronous devices achieve high speed data transfer rates up to 143 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with an advanced 64MBit DRAM process technology.

The device HYB39S13620TQ-7 is designed to comply with all JEDEC standards set for synchronous graphics DRAM products, both electrically and mechanically.

RAS, CAS, WE, DSF and CS are pulsed signals which are examined at the positive edge of each externally applied clock. Internal chip operating modes are defined by combinations of these signals. A ten bit address bus accepts address data in the conventional RAS/CAS multiplexing style. Ten row address bits (A0 - A9) and a bank select BA are strobed with RAS. Column address bits plus a bank select are strobed with CAS.

Prior to any access operation, the CAS latency, burst length and burst sequence must be programmed into the device by address inputs during a mode register set cycle. An Auto Precharge function may be enabled to provide a self-timed row precharge. This is initiated at the end of the burst sequence. In addition, it features the write per bit, the block write and the masked block write functions. By having a programmable Mode register and Special Mode register, the system can select the best suitable modes to maximize its performance.

Operating the two memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 143 MHz is possible depending on burst length, CAS latency and speed grade of the device HYB39S13620TQ-7.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V power supply and are available in 100 pin TQFP package.