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HYB18T512AF

Features: • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O• DRAM organisations with 4, 8 and 16 data in/outputs• Double Data Rate architecture: two data transfers per clock cycle, four internal banks for concurrent operation• CAS Latency: 3, 4 and 5•...

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SeekIC No. : 004368710 Detail

HYB18T512AF: Features: • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O• DRAM organisations with 4, 8 and 16 data in/outputs• Double Data Rate architecture: two data transfer...

HYB18T512AF Data Sheet

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Part Number:
HYB18T512AF
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O
• DRAM organisations with 4, 8 and 16 data in/outputs
• Double Data Rate architecture: two data transfers per clock cycle, four internal banks for concurrent operation
• CAS Latency: 3, 4 and 5
• Burst Length: 4 and 8
• Differential clock inputs (CK and CK)
• Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write data.
• DLL aligns DQ and DQS transitions with clock
•DQS can be disabled for single-ended data strobe operation
• Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS
• Data masks (DM) for write data
• Posted CAS by programmable additive latency for better command and data bus efficiency
• Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality.
• Auto-Precharge operation for read and write bursts
• Auto-Refresh, Self-Refresh and power saving Power-Down modes
• Average Refresh Period 7.8 µs at a TCASE lower than 85 °C, 3.9 µs between 85 °C and 95 °C
• Normal and Weak Strength Data-Output Drivers
• 1K page size for ×4 & ×8, 2K page size for ×16
• Packages:
     P-TFBGA-60-6 for ×4 & ×8 component
     P-TFBGA-84-1 for ×16 components


Specifications

 
Symbol
Parameter
Rating
Units
Notes
VDD
Voltage on VDD pin relative to VSS
-1.0 to +2.3
V
1)
VDDQ
Voltage on VDDQ pin relative to VSS
-0.5 to +2.3
V
1)
VDDL
Voltage on VDDL pin relative to VSS
-0.5 to +2.3
V
1)
VIN, VOUT
Voltage on any pin relative to VSS
-0.5 to +2.3
V
1)
TSTG
Storage Temperature
-55 to +100
1)



Description

    The 512-Mb DDR2 DRAM HYB18T512AF is a high-speed Double-Data-Rate-2 CMOS Synchronous DRAM device containing 536,870,912 bits and internally configured as a quad-bank DRAM. The 512-Mb device is organized as either 32 Mbit × 4 I/O × 4 bank, 16 Mbit ×8I/O × 4bank or 8Mbit × 16 I/O × 4 bank chip. These synchronous devices achieve high speed tra-nsfer rates starting at 400 Mb/sec/pin for general applications.  




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