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HYB18T1G800BFL

Features: • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O• DRAM organizations with 4, 8 and 16 data in/outputs• Double Data Rate architecture: two data transfers per clock cycle four internal banks for concurrent operation• Programmable CAS Latency: 3, 4...

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SeekIC No. : 004368598 Detail

HYB18T1G800BFL: Features: • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O• DRAM organizations with 4, 8 and 16 data in/outputs• Double Data Rate architecture: two data transfer...

HYB18T1G800BFL Data Sheet

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Part Number:
HYB18T1G800BFL
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• 1.8 V ± 0.1 V Power Supply
   1.8 V ± 0.1 V (SSTL_18) compatible I/O
• DRAM organizations with 4, 8 and 16 data in/outputs
• Double Data Rate architecture: two data transfers per clock cycle four internal banks for concurrent operation
• Programmable CAS Latency: 3, 4, 5 and 6
• Programmable Burst Length: 4 and 8
• Differential clock inputs (CK and CK)
• Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write data
• DLL aligns DQ and DQS transitions with clock
• DQS can be disabled for single-ended data strobe operation
• Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS
• Data masks (DM) for write data
• Posted CAS by programmable additive latency for better command and data bus efficiency
• Off-Chip-Driver impedance adjustment (OCD) and On- Die-Termination (ODT) for better signal quality
• Auto-Precharge operation for read and write bursts
• Auto-Refresh, Self-Refresh and power saving Power- Down modes
• Average Refresh Period 7.8 s at a TCASE lower than 85 °C, 3.9 s between 85 °C and 95 °C
• Programmable self refresh rate via EMRS2 setting
• Programmable partial array refresh via EMRS2 settings
• DCC enabling via EMRS2 setting
• Full and reduced Strength Data-Output Drivers
• 1K page size for *4 & *8, 2K page size for *16
• Package: P(G)-TFBGA-68 , P(G)-TFBGA-84 and PG-TFBGA-92
• RoHS Compliant Products1)
• All Speed grades faster than DDR2400 comply with DDR2400 timing specifications when run at a clock rate of 200 MHz.


Specifications

Symbol Parameter
Rating
 Unit Note
Min. Max.
VDD Voltage on VDD pin relative to VSS

-1.0

 +2.3 V 1)
VDDQ Voltage on VDDQ pin relative to VSS

-0.5

 +2.3 V 1)2)
VDDL Voltage on VDDL pin relative to VSS -0.5 +2.3 V 1)2)
VIN,VOUT Voltage on any pin relative to VSS -0.5 +2.3 V 1)
TSTG Storage Temperature -55 +100 1)2)
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.

Attention: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.


Description

The 1-Gbit DDR2 DRAM HYB18T1G800BFL is a high-speed Double-Data-Rate- Two CMOS Synchronous DRAM device, containing 1,073,741,824 bits and internally configured as anoctal quadbank DRAM. The 1-Gbit device is organized as either 32 Mbit ×4 I/O ×8 banks, 16 Mbit ×8 I/O ×8 banks or 8 Mbit ×16 I/O ×8 banks chip. These devices achieve high speed transfer rates starting at 400 Mb/sec/pin for general applications.

The device HYB18T1G800BFL is designed to comply with all DDR2 SDRAM key features:
1. Posted CAS with additive latency,
2. Write latency = read latency - 1,
3. Normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.
    All of the HYB18T1G800BFL control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion.

A 17-bit address bus for ×4 and ×8 organised components and a 16 bit address bus for ×16 components is used to convey row, column and bank address  nformation in a RASCAS multiplexing style.

The DDR2 device HYB18T1G800BFL operates with a 1.8 V ± 0.1 V power supply. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes.

The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode ofoperation.
 
The DDR2 SDRAM HYB18T1G800BFL is available in P(G)-TFBGA-68 and P(G)- TFBGA-84 packages.




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