Features: •High Performance:
| Speed Sorts |
-5
DDR2
-400 |
-3.7
DDR2
-533 |
-3
SDDR2
-667 |
-3
DDR2
-667 |
Units |
| Bin (CL-tRCD-TRP) |
3-3-3 |
4-4-4 |
5-5-5 |
4-4-4 |
tck |
| max. Clock Frequency |
200 |
266 |
333 |
MHz |
| Data Rate 400533667Mb/s/pin |
400 |
533 |
667 |
Mb/s/pin |
| CASLatency (CL) |
3 |
4 |
5 |
4 |
tck |
| tRCD15151512ns |
15 |
15 |
15 |
12 |
ns |
| tRP |
15 |
15 |
15 |
12 |
ns |
| tRAS |
40 |
45 |
45 |
45 |
ns |
| tRC |
55 |
60 |
60 |
57 |
ns |
•1.8V ± 0.1V Power Supply 1.8 V ± 0.1V (SSTL_18) compatible) I/O
•DRAM organisations with 4, 8 and 16 data in/outputs
•Double Data Rate architecture: two data transfers per clock cycle, eight internal banks for concurrent operation
•CAS Latency: 3, 4 and 5
•Burst Length: 4 and 8
DescriptionThe 1Gb Double-Data-Rate-2 (DDR2) DRAMs HYB18T1G400AF are high-speed CMOS Double Data Rate 2 Synchronous DRAM devices con-taining 1,073,741,824 bits and is internally configured as a octal bank DRAM. The 1Gb chip is organized as either 32Mbit x 4 I/O x 8 banks, 16Mbit x 8 I/O x 8 banks or 8Mbit x 16 I/O x 8 banks device. These synchronous devices achieve high speed double-data-rate transfer rates of up to 667 Mb/sec/pin for gen-eral applications.
The chip HYB18T1G400AF is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write latency= read latency -1, (3) normal and weak strength data-output driver, (4) Off-Chip Driver (OCD) impedance adjustment and (5) an ODT (On-Die Termination) function.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK fall- ing). All I/Os are synchronized with a single ended DQS or dif-ferential (DQS, DQS) pair in a source synchronous fashion. A 17 bit address bus for x 4 and x 8 organised components and a 16 bit address bus for x16 components is used to convey row,column and bank address information in a RAS / CAS multi-plexing style.
The DDR2 devices HYB18T1G400AF operate with a 1.8V +/-0.1V power supply and are available in FBGA packages.
An Auto-Refresh and Self-Refresh mode is provided along withvarious power-saving power-down modes.
The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
HYB18T1G400AF Data Sheet
