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HYB18RL25632AC

Features: `256 Megabit (256M)`0.17m process technology`Cyclic bank addressing for maximum data out bandwidth`Organization 8M x 32, 16M x 16 in 8 banks`Non-multiplexed addresses`Non-interruptible sequential bursts of 2 (2-bit prefetch) and 4 (4-bit prefetch), DDR`Up to 600Mb/sec/pin data rate`Progr...

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SeekIC No. : 004368549 Detail

HYB18RL25632AC: Features: `256 Megabit (256M)`0.17m process technology`Cyclic bank addressing for maximum data out bandwidth`Organization 8M x 32, 16M x 16 in 8 banks`Non-multiplexed addresses`Non-interruptible seq...

HYB18RL25632AC Data Sheet

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Part Number:
HYB18RL25632AC
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

`256 Megabit (256M)
`0.17m process technology
`Cyclic bank addressing for maximum data out bandwidth
`Organization 8M x 32, 16M x 16 in 8 banks
`Non-multiplexed addresses
`Non-interruptible sequential bursts of 2 (2-bit prefetch) and 4 (4-bit prefetch), DDR
`Up to 600Mb/sec/pin data rate
`Programmable Read Latency (RL) of 5..6
`Data valid signal (DVLD) activated as Read Data is available
`Data Mask signals (DM0 / DM1) to mask first and second part of write data burst
`IEEE 1149.1 compliant JTAG Boundary Scan
`Pseudo-HSTL 1.8V IO Supply
`Internal autoprecharge
`Refresh requirements: 32ms at 100°C junction temperature (8k refresh for each bank, 64k refresh commands must be issued in total each 32ms)
`Package T-FBGA 144
`2.5V VEXT, 1.8V VDD, 1.8V VDDQ


Specifications

Storage temperature range ................ 55 to + 150 °C
Input/output pins voltage................ 0.3 to VDDQ + 0.3V
Inputs and VREF voltage ................ 0.3 to VDDQ + 0.3V
Power supply voltage VDD .................. 0.3 to + 2.1V
Power supply voltage VEXT .................. 0.3 to + 2.8V
Power supply voltage VDDQ .................. 0.3 to + 2.1V
Junction Temperature ..................... 0°C to 100°C
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.


Description

The Infineon 256M Reduced Latency DRAM (RLDRAM) HYB18RL25632AC contains 8 banks x 32 Mb of memory accessible with 32bit or 16bit I/O's in a double data rate (DDR) format where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high data bandwidth.

RLDRAM HYB18RL25632AC is designed for communication data storages like transmit or receive buffers in telecommunication systems as well as data or instruction cache applications requiring large amounts of memory.




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