HYB18M1G320BF7.5

Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.

The HYB18M1G320BF7.5 is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It is
internally configured as a quad-bank DRAM.

The HYB18M1G320BF7.5 uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate
architecture is essentially a 2n pre fetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single READ or WRITE access for the DDR Mobile-RAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O balls.

The HYB18M1G320BF7.5 is especially designed for mobile applications. It operates from a 1.8V power supply. Power
consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can further be reduced by using the programmable Partial Array Self Refresh (PASR).

A conventional data-retaining Power-Down (PD) mode is available from HYB18M1G320BF7.5 as well as a non-data-retaining Deep Power-Down (DPD) mode. For further power-savings the clock may be stopped during idle periods.

The HYB18M1G320BF7.5 is housed in a 90-ball PG-VFBGA-90-5 package. It is available in Commercial (-0°C to +70°C) and Extended (-25°C to +85°C) temperature range.