HY5V66LF6P

Features: • Voltage: VDD, VDDQ 3.3V supply voltage• All device pins are compatible with LVTTL interface• 60 Ball FBGA (Lead or Lead Free Package)• All inputs and outputs referenced to positive edge of system clock• Data mask function by UDQM, LDQM• Internal four...

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SeekIC No. : 004368346 Detail

HY5V66LF6P: Features: • Voltage: VDD, VDDQ 3.3V supply voltage• All device pins are compatible with LVTTL interface• 60 Ball FBGA (Lead or Lead Free Package)• All inputs and outputs refe...

floor Price/Ceiling Price

Part Number:
HY5V66LF6P
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/10/30

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Product Details

Description



Features:

• Voltage: VDD, VDDQ 3.3V supply voltage
• All device pins are compatible with LVTTL interface
• 60 Ball FBGA (Lead or Lead Free Package)
• All inputs and outputs referenced to positive edge of system clock
• Data mask function by UDQM, LDQM
• Internal four banks operation
• Auto refresh and self refresh
• 4096 Refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency; 2, 3 Clocks
• Burst Read Single Write operation



Specifications

Parameter
Symbol
Rating
Unit
Operating Temperature
TA
0 to 70
Storage Temperature
TSTG
-55 ~ 125
Voltage on Any Pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD
1.0
W
Ball Soldering Temperature & Time
TSOLDER
260`10
`sec



Description

The HY5V66LF6P series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V66E(L)F6(P) is organized as 4banks of 1,048,576 x 16.

HY5V66LF6P is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

HY5V66LF6P Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule)




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