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HY5PS12821L

Features: • VDD=1.8V• VDDQ=1.8V +/- 0.1V• All inputs and outputs are compatible with SSTL_18 interface• Fully differential clock inputs (CK, /CK) operation• Double data rate interface• Source synchronous-data transaction aligned to bidirectional data strobe (DQS...

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SeekIC No. : 004368332 Detail

HY5PS12821L: Features: • VDD=1.8V• VDDQ=1.8V +/- 0.1V• All inputs and outputs are compatible with SSTL_18 interface• Fully differential clock inputs (CK, /CK) operation• Double data...

HY5PS12821L Data Sheet

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Part Number:
HY5PS12821L
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• VDD=1.8V
• VDDQ=1.8V +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 3, 4, 5 and 6 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 60ball FBGA(x4/x8) & 84ball FBGA(x16)
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Read Data Strobe suupported (x8 only)
• Self-Refresh High Temperature Entry


Specifications

Symbol Parameter Rating Units
VDD
Voltage on VDD pin relative to Vss 1
- 1.0 V ~ 2.3 V
V
VDDQ
Voltage on VDDQ pin relative to Vss 1
- 0.5 V ~ 2.3 V
V
VDDL
Voltage on VDDL pin relative to Vss 1
- 0.5 V ~ 2.3 V
V
VIN,VOUT
 Voltage on any pin relative to Vss 1
- 0.5 V ~ 2.3 V
V
TSTG
 Storage Temperature 1,2
-55 to +100
°C

1. . Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.  Storage Temperature is the case surface temperature on the denter/top side of the DRAM. For the measurement conditions.Please refer to JESD51-2 standard




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