HY5PS121621FP-Y5

The HY5PS121621FP-Y5 is a kind of 512Mb DDR2 SDRAM. It is organized as a 32Mbit*16 device. It is available in 84ball FBGAs(*16) package. Then is some information about the operating frequency: tCK=3 ns; CL=5 Clk; tRCD=4 Clk; tRP=5 Clk.

There are some HY5PS121621FP-Y5 key features as follows. (1) all inputs and outputs are compatible with SSTL_18 interface; (2) fully differential clock inputs (CK, /CK) operation; (3) double data rate interface; (4) DM mask write data-in at the both rising and falling edges of the data strobe;(5) all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock; (6) programmable CAS latency 3, 4, 5 and 6 supported; (7)programmable additive latency 0, 1, 2, 3, 4 and 5 supported; (8) programmable burst length 4/8 with both nibble sequential and interleave mode; (9) internal four bank operations with single pulsed RAS; (10) auto refresh and self refresh supported; (11) tRAS lockout supported; (12) 8K refresh cycles/64 ms; (13) off chip driver impedance adjustment supported.

The following is about HY5PS121621FP-Y5 absolute maximum ratings. (1): VDD (voltage on VDD pin relative to VSS) is from -1.0 to +2.3 V; (2): VDDQ (voltage on VDDQ pin relative to VSS) is from -0.5 to +2.3 V; (3): VDDL (voltage on VDDL pin relative to VSS) is from -0.5 to +2.3 V; (4): VIN, VOUT (voltage on any pin relative to VSS) is from -0.5 to 2.3 V; (5) TSTG (storage temperature) is from -55 to +100; (5) TOPER (operating temperature) is from 0 to +85.