Features: • Single 3.3±0.3V power supply
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch
• All inputs and outputs referenced to positive edge of system clock
• Data mask function by DQM
• Internal four banks operation
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 ClocksPinout
Specifications
| Parameter |
Symbol |
Rating |
Unit |
| Ambient Temperature |
TA |
0 ~ 70 |
|
| Storage Temperature |
TSTG |
-55 ~ 125 |
|
| Voltage on Any Pin relative to VSS |
VIN, VOUT |
-1.0 ~ 4.6 |
V |
| Voltage on VDD relative to VSS |
VDD, VDDQ |
-1.0 ~ 4.6 |
V |
| Short Circuit Output Current |
IOS |
50 |
mA |
| Power Dissipation |
PD |
1 |
W |
| Soldering Temperature .Time |
TSOLDER |
260 .10 |
°C .Sec |
DescriptionThe HY57V64820HGTP is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memoryapplications which require large memory density and high bandwidth. HY57V64820HG is organized as 4banks of 2,097,152x8.
HY57V64820HGTP is offering fully synchronous operation referenced to a positive edge of the clock. All inputsand outputs are synchro-nized with the rising edge of the clock input. The data paths are internallypipelined to achieve very high bandwidth. All input and outputvoltage levels are compatible with LVTTL.
HY57V64820HGTP Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive reador write cycles initiated bya single control command (Burst length of 1,2,4,8 or Full page), and theburst count sequence(sequential or interleave). A burst of reador write cycles in progress can be terminated by aburst terminate command or can be interrupted and replaced by a new burst read orwrite command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
HY57V64820HGTP Data Sheet
