HY57V281620HC(L)T

The Hynix HY57V281620HC(L)T is a 134 , 217,728 bit CMOS Synchronous DRAM , ideally suited for the Mobile applications which require low power consumption and extended temperature range. It is organized as 4 banks  f 2 ,097,152 x 16.

HY57V281620HC(L)T is offering fully synchronous operation referenced to apositive edge of the clock . All inputs and outputs are syn-chronized with the rising edge of the clock input . The data paths are internally pipelined to achieve very high bandwidth . All input and output voltage levels are compatible with LVTTL .

HY57V281620HC(L)T Programmable options include the length of pipeline(Read latency of 2 or 3),the number of consecutive read or write cycles initiated by a single control command(Burst length of 1 ,2,4 , 8, or full page) ,and the burst count sequence(sequential or interleave).Aburst of read or  write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a`2N` rule.)