Features: • Fabricated on Honeywell's Radiation Hardened 0.65m Leff (0.55m for 3.3v device) RICMOSTM Silicon On Insulator (SOI-IV) process
• Choice of supply voltage at 5v or 3.3v with 5v tolerant inputs.
• TTL and CMOS Compatible I/O
• 3.3 MIPS DAIS Mix Including Floating Point
• Maximum Clock Rates 40 Mhz, Fully Static
• Separate Address and Data I/O Busses
• Two Programmable Timers
• Trigger-go Counter
• Sixteen Levels of Vectored Interrupts
• I/O Maintenance Console Interface
• Expanded Addressing to 1Meg with MMU
• Total Dose Hardness 1x105 rad(Si)
• Soft Error Rate < 1x10-9 Errors/Bit-Day- Projected
• No Latchup
• Low PowerDescriptionThe HX1750 is a true single chip implementation of the MIL-STD-1750A instruction set architecture, fabricated on Honeywell's RICMOSTM Silicon on Insulator (SOI-IV) process. It combines a fast 16 bit microprocessor, a 40 bit floating point processor, counters, timers and other peripheral interface logic all on a single chip. Advanced architectural features, innovative circuit design, and the high density and performance characteristics of the SOIIV process enable device operation up to 40 MHz over the full military temperature range, even after exposure to ionizing radiation. The Soft Error Rate (SER) is less than 1x10-11 Errors/Bit-Day in the Adams 90% worst case environment.
The HX1750 offers a wide range of features that provide for ease of use, versatility and minimum external components. Simplified memory interface and adjustable cycle times allows the use of slower, low cost memory devices.
Most of the options in the MIL-STD-1750A standard are implemented on the HX1750 chip as listed below:
• Discrete I/O Commands
• DMA Commands
• Console Interface Commands
• Programmed I/O Commands
• IOIC Registers
• Expanded Memory Addressing
• Memory Block Protect
• Two Interval Timers
• Trigger Go Counter
• Start-ROM Support
Several features are incorporated into the HX1750 to simplify the system interface, minimize external components, reduce external memory speed requirements, and ease software development.
• A separate address and data bus eliminates the need for external PIC chip, address demultiplexers and latches.
• Fast address and data buffers provide signals early in the cycle allowing use of slower, low cost memories.
• Enhanced Maintenance Console.
• Standard memory addressing to 64K expanded to 1Meg with MMU.
• Access Lock and Key implemented.
• Simple DMA control implemented
• Coprocessor supported in separate address space.
• Variable System clock internal programmable divider (tie Scale pin high or low) cuts the internal bus cycle time in half.
• Data, Instruction, and I/O access time independently programmable.
•Full synchronous or asynchronous operation programmable wait states for instructions, data, and I/O. Asynchronous operation is slaved to an external RDY signal.
• Enhanced set of Built-In-Functions.
• Enhanced Configuration Register.
• Enhanced Maintenance Console with single step operation.
The processor executes all mandatory MILSTD- 1750A instructions including floating point. Interrupts, fault handling, memory expansion, and I/O and the optional instructions related to these operations are also supported in accordance with MIL-STD- 1750A. All instructions are re-startable after access faults for true demand paging operation.
HX1750 Data Sheet
