Features: ·5V CMOS inputs·64 outputs per device·Up to 60V output voltage·Capable of 4 output pulse widths·PWM gray shade conversion·Two 2-bit data buses·28 MHz data throughput rate·Pin-programmable shift direction (DIR)·Integrated high-voltage CMOS technology·Optimized layout for COG useSpecificat...
HV62106: Features: ·5V CMOS inputs·64 outputs per device·Up to 60V output voltage·Capable of 4 output pulse widths·PWM gray shade conversion·Two 2-bit data buses·28 MHz data throughput rate·Pin-programmable ...
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·5V CMOS inputs
·64 outputs per device
·Up to 60V output voltage
·Capable of 4 output pulse widths
·PWM gray shade conversion
·Two 2-bit data buses
·28 MHz data throughput rate
·Pin-programmable shift direction (DIR)
·Integrated high-voltage CMOS technology
·Optimized layout for COG use
Supply voltage, VDD |
-0.5V to +7.5V |
Supply voltage, VPP |
-0.5V to +70V |
Logic input levels |
-0.5V to VDD + 0.5V |
Operating temperature range |
-40 to +85 |
Storage temperature range |
-65 to +150 |
The HV62106 is a 64-channel column driver IC designed for gray shade flat panel displays. Using Supertex's unique HVCMOS® technology, it is capable of providing gray shading by pulse width modulation (PWM) conversion. A high level on the chip select input enables the IC to load data into a set of input data latches. This input data, in two groups of two, are latched into the input data latches on both edges of the Shift Clock.
The data stored in these input data latches is transferred to a set of output data latches on the rising edge of Load Count. After the input data registers are full, a chip select output signal is provided for enabling the next IC in the chain. A master binary counter of HV62106 is reset with a high level on Load Count and is incremented on the rising edge of Count Clock. The data stored in the output data latches is compared to the contents of the master counter. The output of the comparator drives the high voltage output devices.
The higher the binary number in the output data latches of HV62106, the longer the pulse width will be on the corresponding output. DIR is a shift-direction-select input which is provided to interchange the direction of the latched data inputs. When the DIR input is high, CS2 becomes chip select input and data is latched into the data latches in the sequence of HVOUT1 to HVOUT64. When the DIR input is low, CS1 becomes chip select input and data is latched into the data latches in the sequence of HVOUT64 to HVOUT1. DIN1 and DIN2 load in data for odd number of outputs. DIN3 and DIN4 load in data for even number of outputs.