HV570

Features: ·HVCMOS® technology·5.0V CMOS Logic·Output voltage up to -85V·Output current source control·16MHz equivalent data rate·Latched data outputs·Foreward and reverse shifting options (DIR pin)·Diode to VDD allows effi cient power recoveryPinoutSpecifications Parameter Value ...

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HV570 Picture
SeekIC No. : 004367562 Detail

HV570: Features: ·HVCMOS® technology·5.0V CMOS Logic·Output voltage up to -85V·Output current source control·16MHz equivalent data rate·Latched data outputs·Foreward and reverse shifting options (DIR p...

floor Price/Ceiling Price

Part Number:
HV570
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

·HVCMOS® technology
·5.0V CMOS Logic
·Output voltage up to -85V
·Output current source control
·16MHz equivalent data rate
·Latched data outputs
·Foreward and reverse shifting options (DIR pin)
·Diode to VDD allows effi cient power recovery



Pinout

  Connection Diagram


Specifications

Parameter Value
Supply voltage, VDD1 -0.5V to +7.5V
Output voltage , VPP1 VDD + 0.5V to -95V
Logic input levels1 -0.3V to VDD + 0.3V
Ground current2 1.5A
Continuous total power dissipation3 1200mW
Continuous total power dissipation3 -40°C to +85°C
Storage temperature range -65°C to +150°C
Lead temperature 1.6mm from
case for 10 seconds
260°C
1. All voltages are referenced to VSS
2. Limited by the total dissipated in the package.
3. For operation above 25°C ambiant derate linearly to maximum operating temperature at 20mW/°C.



Description

The HV570 is a low-voltage serial to high-voltage parallel converter with P-channel open drain outputs. This device has been designed for use as a driver for plasma panels. The device has two parallel 32-bit shift registers, permitting data rates twice the speed of one (they are clocked together).

HV570 also has 64 latches and control logic to perform the blanking of the outputs. HVOUT1 is connected to the fi rst stage of the fi rst shift register through the blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock.

The DIR pin causes CCW shifting when connected to VSS, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output refl ects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the LE (latch enable), or the BL (blanking) inputs. Transfer of data from the shift registers to latches occurs when the LE input is high. The data in the latches is stored when LE is low. The HV570 has 64 channels of output constant current sourcing capability. They are adjustable from 0.1 to 2.0mA through one external resistor or a current source.




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