HV4937

Features: HVCMOS® Technology Output voltages up to -375V Source current minimum 0.25mA Shift register speed 6 MHz Latched outputs CMOS compatible inputs Forward and reverse shifting optionsSpecificationsSupply voltage, VDD +0.5V to -9VSupply voltage, VPP +0.5V to -400VLogic input levels +0....

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HV4937 Picture
SeekIC No. : 004367539 Detail

HV4937: Features: HVCMOS® Technology Output voltages up to -375V Source current minimum 0.25mA Shift register speed 6 MHz Latched outputs CMOS compatible inputs Forward and reverse shifting optionsSpeci...

floor Price/Ceiling Price

Part Number:
HV4937
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

 HVCMOS® Technology
Output voltages up to -375V
Source current minimum 0.25mA
Shift register speed 6 MHz
Latched outputs
CMOS compatible inputs
Forward and reverse shifting options



Specifications

Supply voltage, VDD                              +0.5V to -9V
Supply voltage, VPP                           +0.5V to -400V
Logic input levels                         +0.5V to VDD -0.5V
Ground current                                                0.75A
Continuous total power dissipation2          1200mW
Operating temperature range       -40°C to +85°C
Storage temperature range        -65°C to +150°C



Description

Not recommended for new designs.

The HV4937 is a low voltage serial to high voltage parallel converter with open drain outputs. It has been designed especially for use as a driver for electrostatic printers.

This device HV4937 consists of a 64-bit shift register, 64 latches, a latch enable (LE), and an output enable (OE). Data is shifted through the shift register on the high to low transition of the clock. When the DIR pin is set high, the HV49 shifts in the counterclockwise direction when viewed from the top of the package. When the DIR pin is set low, the HV4937 shifts in the clockwise direction. A serial data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register. Operation of the shift register is not affected by the LE or the OE inputs. Transfer of data from the shift register to the latch occurs when the LE input is high. The data in the latch is stored when LE is low.




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