Features: · Processed with HVCMOS Technology· Output voltages to -300V· Source current minimum 60 mA· Shift register speed 8 MHz· Polarity and blanking inputs· CMOS compatible inputs· Forward and reverse shifting options· 44-lead plastic and ceramic surface mount packages· Hi-Rel processing availa...
HV4530: Features: · Processed with HVCMOS Technology· Output voltages to -300V· Source current minimum 60 mA· Shift register speed 8 MHz· Polarity and blanking inputs· CMOS compatible inputs· Forward and re...
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Supply voltage, VDD +0.5V to -16V
Off state output voltage HV4630 +0.5V to -315V
HV4622 +0.5V to -240V
Logic input levels +0.5V to VDD - 0.3V
Ground current2 1.5A
Continuous total power dissipation 3 1200mW
Operating temperature range -40 to +85
Storage temperature range -65 to +150
Lead temperature 1.6mm (1/16 inch) 260
from case for 10 seconds
Notes:
1. All voltages are referenced to VSS.
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C for plastic and at 15mW/°C for ceramic.
The HV4530 and HV46 are low-voltage serial to high-voltage parallel converters with P-Channel open drain outputs. These devices have been designed for use as drivers for AC-electroluminescent displays. They can also be used in any application requiring multiple output high-voltage current source capabilities such as driving inkjet and electrostatic print heads, plasma panels, or vacuum fluorescent displays.
These devices HV4530 consist of a 32-bit shift register, 32 data latches, and control logic to perform polarity and blanking functions. Data is shifted through the shift register on the logic high-to-low transition of the clock. The HV4530 shifts in the counterclockwise direction when viewed from the top of the package and the HV46 shifts in the clockwise direction. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register. The data in the shift register is latched when the latch enable pin is brought to logic high and then returned to ground. If the latch enable pin is held high, the latch becomes transparent and the shift register data is directly reflected in the outputs.
For applications requiring active pull down as well as pull up, the HV4530 and HV46 can be paired with the HV55 and HV56 devices, respectively.