Features: HVCMOS® technology Output voltages up to 275V Low power level shifting Shift register speed 6MHz @ VDD = 5V Latched data outputs Output polarity and blanking CMOS compatible inputs Forward and reverse shifting optionsPinoutSpecificationsSupply voltage, VDD..............-0.5V to +6VS...
HV3527: Features: HVCMOS® technology Output voltages up to 275V Low power level shifting Shift register speed 6MHz @ VDD = 5V Latched data outputs Output polarity and blanking CMOS compatible inputs Fo...
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Supply voltage, VDD..............-0.5V to +6V
Supply voltage, VPP.............. VDD to 300V
Logic input levels ...........-0.5V to VDD +0.5V
Ground current2 .....................1.5A
High voltage supply current2 ............. 1.3A
Continuous total power dissipation3 ......1200mW
Operating temperature range ........0 to +70
Storage temperature range........-65 to +150
Notes:
1. All voltages are referenced to GND.
2. Connection to all power and ground pads is required. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to 85 at 15mW/.
(Not recommended for new designs. Please use HV507 with improved performance.)
The HV3527 is a low voltage serial to high voltage parallel converter with push-pull outputs. This device has been designed for use as a printer driver for electrostatic applications. It can also be used in any application requiring multiple output high voltage, low current sourcing and sinking capabilities.
The device HV3527 consists of a 64-bit shift register, 64 latches, and control logic to perform the polarity select and blanking of the outputs. A DIR pin controls the direction of data shift through the device. With DIR grounded, DIOA is Data-In and DIOB is Data-Out; data is shifted from HVOUT64 to HVOUT1. When DIR is at logic high, DIOB is Data-In and DIOA is Data-Out: data is then shifted from HVOUT1 to HVOUT64. Data is shifted through the shift register on the low to high transition of the clock. Data output buffers are provided for cascading devices. Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) is high. The data in the latch is stored during LE transition from high to low.
A bias pin is used to ensure that the device HV3527 operates at full VPP voltage.