HSTL16918

NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This current flows only when the output is in the high state and V_O > V_CC.
4. The package thermal impedance is calculated in accordance with JESD 51.

The HSTL16918 is a 9-bit to 18-bit D-type latch designed for 3.15 to 3.45 V V_CC operation. The D inputs accept HSTL levels and the Q outputs provide LVTTL levels.

The HSTL16918 is particularly suitable for driving an address bus to two banks of memory. Each bank of nine outputs is controlled with its own latch-enable (LE) input.

Each of the nine D inputs is tied to the inputs of two D-type latches that provide true data (Q) at the outputs. While LE is LOW the Q outputs of the corresponding nine latches follow the D inputs. When LE is taken HIGH, the Q outputs are latched at the levels set up at the D inputs.

The HSTL16918 is characterized for operation from 0 to +70 °C.