HSD2M64B2

Features: • Part IdentificationHSD2M64B2-F/10 :100MHzHSD2M64B2-F/8 :125MHz* F : Auto Self-Refresh with Low Power• Burst mode operation• Auto & self refresh capability (4096 Cycles/64ms)• LVTTL compatible inputs and outputs• Single 3.3V ±0.3V power supply• MR...

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SeekIC No. : 004366006 Detail

HSD2M64B2: Features: • Part IdentificationHSD2M64B2-F/10 :100MHzHSD2M64B2-F/8 :125MHz* F : Auto Self-Refresh with Low Power• Burst mode operation• Auto & self refresh capability (4096 Cyc...

floor Price/Ceiling Price

Part Number:
HSD2M64B2
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/8/14

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Product Details

Description



Features:

• Part Identification
HSD2M64B2-F/10 :100MHz
HSD2M64B2-F/8 :125MHz
* F : Auto Self-Refresh with Low Power
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
• JEDEC standard 144-Pin SO-DIMM
• All inputs are sampled at the positive going edge of the system clock
• The used device is 512Kx32Bitx4Banks SDRAM





Specifications

PARAMETER SYMBOL RATING
Voltage on Any Pin Relative to Vss

Voltage on Vcc Supply Relative to Vss

Power Dissipation

Storage Temperature

Short Circuit Output Current
VIN ,OUT

Vcc

PD

TSTG

IOS
-1V to 4.6V

-1V to 4.6V

2W

-55 to 150

100mA

Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.






Description

The HSD2M64B2 is a 2M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists of two CMOS 512K x 32 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 144-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD2M64B2 is a SO-DIMM(Small Outline Dual in line Memory Module) and is intended for mounting into 144-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.






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