HSD16M64D16A

• Part Identification HSD16M64D16A-F/10L : 100MHz (CL=3) HSD16M64D16A-F/10 : 100MHz (CL=2) HSD16M64D16A-F/12 : 125MHz (CL=3) HSD16M64D16A-F/13 : 133MHz (CL=3) F means Auto & Self refresh with Low-Power (3.3V)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• The used device is 8M x 8bit x 4Banks SDRAM

Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

The HSD16M64D16A is a 16M x 64 bit Synchronous Dynamic RAM high-density memory module. The module consists of sixteen CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy. Two 0.33uF-decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD16M64D16A is a DIMM (Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.