HS-81C55RH

Features:

* Devices QML Qualified in Accordance with MIL-PRF-38535
* Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95818 and Intersil' QM Plan
* Radiation Hardened EPI-CMOS
   - Parametrics Guaranteed 1 x 10⁵  RAD(Si)
   - Transient Upset > 1 x 10⁸  RAD(Si)/s
   - Latch-Up Free > 1 x 10¹²  RAD(Si)/s
* Electrically Equivalent to Sandia SA 3001
* Pin Compatible with Intel 8155/56
* Bus Compatible with HS-80C85RH
* Single 5V Power Supply
* Low Standby Current 200A Max
* Low Operating Current 2mA/MHz
* Completely Static Design
* Internal Address Latches
* Two Programmable 8-Bit I/O Ports
* One Programmable 6-Bit I/O Port
* Programmable 14-Bit Binary Counter/Timer
* Multiplexed Address and Data Bus
* Self Aligned Junction Isolated (SAJI) Process
* Military Temperature Range -55  to +125


Pinout




Specifications

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to V_DD+0.3V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65  to +150
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300
Typical Derating Factor. . . . . . . . . . . . 2mA/MHz Increase in IDDOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1


Description

The HS-81C55RH/56RH are radiation hardened RAM and I/O chips fabricated using the Intersil radiation hardened Self-
Aligned Junction Isolated (SAJI) silicon gate technology. Latch-up free operation is achieved by the use of epitaxial
starting material to eliminate the parasitic SCR effect seen in conventional bulk CMOS devices.

The HS-81C55RH/56RH is intended for use with the HS-80C85RH radiation hardened microprocessor system. The RAM portion is designed as 2048 static cells organized as 256x 8. A maximum post irradiation access time of 500nsallows
the HS-81C55/56RH to be used with the HS-80C85RH CPU without any wait states. The HS-81C55RH requires an active low chip enable while the HS-81C56RH requires an active high chip enable. These chips are designed for operation utilizing a single 5V power supply.