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HM67S18258

Features: · 3.3V ± 5% Operation· LVCMOS Compatible Input and Output· Synchronous Operation· Internal self-timed Late Write· Asynchronous G Output Control· Byte Write Control (2 byte write selects, one for each 9 bits)· Power down mode is provided· Differential PECL Clock Inputs· Boundary Scan· Pro...

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SeekIC No. : 004363615 Detail

HM67S18258: Features: · 3.3V ± 5% Operation· LVCMOS Compatible Input and Output· Synchronous Operation· Internal self-timed Late Write· Asynchronous G Output Control· Byte Write Control (2 byte write selects, o...

HM67S18258 Data Sheet

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Part Number:
HM67S18258
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

·  3.3V ± 5% Operation
·  LVCMOS Compatible Input and Output
·  Synchronous Operation
·  Internal self-timed Late Write
·  Asynchronous G Output Control
·  Byte Write Control
     (2 byte write selects, one for each 9 bits)
·  Power down mode is provided
·  Differential PECL Clock Inputs
·  Boundary Scan
·  Protocol Single Clock Resister-Latch Mode


Pinout

Connection Diagram


Specifications

Parameter
Symbol
Value
Unit
Note
supply voltage
VDD
0.5 to + 4.6
V
1
Output Supply Voltage
VDDQ
0.5 to VDD+0.5
V
1, 4
Voltage on any pin
VIN
0.5 to VDD+0.5
V
1, 4
Operating Temperature
Ta
0 to 70 (Tj max = 110)
°C
  
Storage Temperature
ToprTstg (bias)
55 to 125
°C
  
Input Latchup Current
ILI
±200
mA
  
Output Current per pin
Iout
±25
mA
  

Notes: 1. All voltage are referenced to VSS.
2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional
operation should be restricted the Operation Conditions. Exposure to higher than recommended
voltages for extended periods of time could affect device reliability.
3. These Bi-CMOS memory circuits have been designed to meet the DC and AC specifications
shown in the tables after thermal equilibrium has been established.
4. Not exceed 4.6 V
5. Power Up Initialization
The following supply voltage application sequence is recommended: VSS, VDD then VDDQ.
Remember according to the Absolute Maximum Ratings table, VDDQ is not to exceed VDD + 0.5 V,
whatever the instantaneous value of VDD.


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