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HIP7030A2

Features: • Fully Supports VPW Specifications of SAE J1850 Standard for Class B Data Communications Network Interface• On-Chip Memory• 176 Bytes of RAM• 2110 Bytes of User ROM• 13 Bidirectional I/O Lines• 16-Bit Timer with Capture and Compare Registers• Se...

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SeekIC No. : 004362780 Detail

HIP7030A2: Features: • Fully Supports VPW Specifications of SAE J1850 Standard for Class B Data Communications Network Interface• On-Chip Memory• 176 Bytes of RAM• 2110 Bytes of User RO...

HIP7030A2 Data Sheet

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Part Number:
HIP7030A2
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Fully Supports VPW Specifications of SAE J1850
   Standard for Class B Data Communications Network Interface
• On-Chip Memory
• 176 Bytes of RAM
• 2110 Bytes of User ROM
• 13 Bidirectional I/O Lines
• 16-Bit Timer with Capture and Compare Registers
• Serial Peripheral Interface (SPI) System
• Watchdog Timer and Slow Clock Detect
• 10MHz Operating Frequency (5.0MHz Internal Bus
   Frequency) at 5V
• Built-In-Test Bootstrap Mode with 242 Bytes of ROM
• Two Channel Analog Comparator
• On-Chip Oscillator Amplifier
• 8-Bit CPU Architecture
• Power-Saving STOP, WAIT and Data Retention Modes
• Full -40oC to 125oC Operating Range
• Single 3.0V to 6.0V Supply
• 28 Lead Dual-In-Line and Small Outline Plastic Packages


Pinout

Connection Diagram


Specifications

Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
Input or Output Voltage
Pins with VDD Diode . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Pins without VDD Diode . . . . . . . . . . . . . . . . . . . . . .  . -0.3V to +10V
Current Drain Per Pin, I (Excluding VDD and VSS) . . . . . . . .. . . 25mA
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265
ESD Classification . . . . . . . . . . . . . . . . . . . . . .  . . .  . . . .  . . . Class 2
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9000 Gates
Thermal Resistance (Typical) qJA
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 60oC/W
Plastic SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  75oC/W
Maximum Package Power Dissipation at +125
DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  415mW
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  325mW
Operating Temperature Range (TA) . . . . . . . . . . . . .-40  to +125
Storage Temperature Range (TSTG). . . . . . . . . . . . .-65  to +150
Junction Temperature . . . . . . . . . . . . . . . . . . . . . .  .. . . . . . . . +150


Description

The HIP7030A2 HCMOS Microcomputer is a member of the CDP68HC05 family of low-cost single-chip microcomputers. The integrated hardware functions provide the system designer with a complete set of building blocks for implementing a "Class B" multiplexed communications network interface, which fully conforms to the VPW Multiplexed Wiring protocol specified in SAE Recommended Practice J1850. This 8-bit microcomputer unit (MCU) contains an onchip oscillator, CPU, 176 bytes of RAM, 2110 bytes of user ROM, 13 I/O lines, a J1850 Variable Pulse Width Symbol Encoder/Decoder (VPW SENDEC) system, a Serial Peripheral Interface (SPI) system, a two channel analog Comparator, a Watchdog Timer, a Slow Clock Detect, and a 16-bit Timer. The static HIP7030A2 HCMOS design allows operation at input frequencies up to 10MHz (5MHz internal clock).




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